Semiconductor assemblies, methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates

ABSTRACT

The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer. The invention encompasses a method of forming a pair of transistors associated with a semiconductor substrate. First and second regions of the substrate are defined. A first oxide region is formed to cover the first region of the substrate, and to not cover the second region of the substrate. Nitrogen is formed within the first oxide region, and a first conductive layer is formed over the first oxide region. After the first conductive layer is formed, a second oxide region is formed over the second region of the substrate. A second conductive layer is formed over the second oxide region. The first conductive layer is patterned into a first transistor gate, and the second conductive layer is patterned into a second transistor gate. First source/drain regions are formed proximate the first transistor gate, and the second source/drain regions are formed proximate the second transistor gate. The invention also encompasses semiconductor assemblies.

TECHNICAL FIELD

[0001] The invention pertains to methods of forming structures oversemiconductor substrates, and in particular embodiments pertains tomethods of forming transistors associated with semiconductor substrates.The invention also pertains to semiconductor assemblies.

BACKGROUND OF THE INVENTION

[0002] There are numerous applications in semiconductor processing inwhich it is desired to form conductive layers over oxides. For instance,transistor structures frequently comprise conductive layers formed oversilicon dioxide (commonly referred to as a gate oxide). In someinstances, the conductive materials comprise conductively doped silicon,and in such instances dopant can occasionally migrate through the oxideinto an underlying substrate. In particular transistor devices, suchdopant migration can be problematic. For instance, PMOS devices comprisean n-type channel region underneath a gate oxide, and can comprisep-type doped silicon over the gate oxide. If p-type dopant migrates fromthe silicon, through the oxide, and into the underlying substrate itwill change the doping within the n-type channel. Such change canaffect, and even destroy, electrical properties of the transistor.Accordingly, it can be desired to alleviate dopant migration relative toPMOS devices.

[0003] In contrast to the above-discussed problems which can beassociated with PMOS devices, dopant migration is typically notproblematic relative to NMOS devices. However, NMOS devices can havetheir own associated problems. For instance, it can be desired to formgate oxide for NMOS devices which is thicker than that utilized for PMOSdevices. Such can be problematic in semiconductor wafer processing, inthat both NMOS devices and PMOS devices are frequently formed over thesame wafer. It would be desired to develop methodology which enablesdifferent gate oxide thicknesses to be associated with differenttransistors on the same wafer, and in particular applications desired todevelop methodology to enable NMOS transistors to have thicker gateoxide than PMOS transistors.

SUMMARY OF THE INVENTION

[0004] In one aspect, the invention encompasses a method of forming astructure over a semiconductor substrate. A silicon dioxide containinglayer is formed across at least some of the substrate. Nitrogen isformed within the silicon dioxide containing layer. Substantially all ofthe nitrogen within the silicon dioxide is at least 10 Å above thesubstrate. After the nitrogen is formed within the silicon dioxidelayer, conductively doped silicon is formed on the silicon dioxidelayer.

[0005] In another aspect, the invention encompasses a method of forminga pair of transistors associated with a semiconductor substrate. Firstand second regions of the substrate are defined. A first oxide region isformed to cover at least some of the first region of the substrate, andto not cover the second region of the substrate. Nitrogen is formedwithin the first oxide region. After the nitrogen is formed, a firstconductive layer is formed over the first oxide region. The firstconductive layer does not cover the second region of the substrate.After the first conductive layer is formed, a second oxide region isformed over the second region of the substrate. A second conductivelayer is formed over the second oxide region. The first conductive layeris patterned into a first transistor gate, and the second conductivelayer is patterned into a second transistor gate. First source/drainregions are formed proximate the first transistor gate, and the secondsource/drain regions are formed proximate the second transistor gate. Inother aspects, the invention pertains to semiconductor assemblies.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0007]FIG. 1 is a diagrammatic, cross-sectional view of semiconductorwafer fragments at a preliminary processing step of a method of thepresent invention.

[0008]FIG. 2 is a view of the FIG. 1 wafer fragments shown at aprocessing step subsequent to that of FIG. 1.

[0009]FIG. 3 is a view of the FIG. 1 wafer fragments shown at aprocessing step subsequent to that of FIG. 2.

[0010]FIG. 4 is a view of the FIG. 1 wafer fragments shown at aprocessing step subsequent to that of FIG. 3.

[0011]FIG. 5 is a view of the FIG. 1 wafer fragments shown at aprocessing step subsequent to that of FIG. 4.

[0012]FIG. 6 is a view of the FIG. 1 wafer fragments shown at aprocessing step subsequent to that of FIG. 5.

[0013]FIG. 7 is a view of the FIG. 1 wafer fragments shown at aprocessing step subsequent to that of FIG. 6.

[0014]FIG. 8 is a diagrammatic, cross-sectional view of an apparatuswhich can be utilized in methodology of the present invention.

[0015]FIG. 9 is a diagrammatic, cross-sectional view of anotherapparatus which can be utilized in methodology of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0017]FIG. 1 shows a semiconductor wafer 10 at a preliminary processingstep of the present invention. Wafer 10 comprises a substrate 16 whichis divided into a first region 12 and a second region 14. Substrate 16can comprise, for example, monocrystalline silicon lightly doped with abackground p-type dopant. To aid in interpretation of the claims thatfollow, the terms “semiconductive substrate” and “semiconductorsubstrate” are defined to mean any construction comprisingsemiconductive material, including, but not limited to, bulksemiconductive materials such as a semiconductive wafer (either alone orin assemblies comprising other materials thereon), and semiconductivematerial layers (either alone or in assemblies comprising othermaterials). The term “substrate” refers to any supporting structure,including, but not limited to, the semiconductive substrates describedabove.

[0018] Regions 12 and 14 can correspond to differently-doped regions ofsubstrate 16. For instance, region 12 can correspond to a portion ofsubstrate 16 having a heavier concentration of n-type conductivityenhancing dopant than p-type conductivity enhancing dopant, and canaccordingly be referred to as an n-type doped region. Further, region 14can correspond to a region of substrate 16 wherein the p-type dopantconcentration is heavier than any n-type dopant concentration, and canaccordingly be referred to as a p-type region of substrate 10. In orderto emphasize this aspect of the invention and assist in the descriptionthat follows, substrate 16 of region 12 is labeled with an “n”, s andregion 14 is labeled with a “p”. It is to be understood that the showndoping of regions 12 and 14 corresponds to a particular embodiment ofthe present invention, and that other embodiments are encompassedwherein both of regions 12 and 14 are similarly doped, includingembodiments wherein regions 12 and 14 are both heavier doped with n-typedopant than p-type dopant, as well as embodiments wherein regions 12 and14 are both heavier doped with p-type dopant than n-type dopant.

[0019] In particular embodiments of the present invention, regions 12and 14 correspond to portions of a semiconductor memory assembly, and insuch embodiments regions 12 and 14 can both correspond to memory arrayregions, or can both correspond to regions peripheral to a memory arrayregions, or alternatively one of regions 12 and 14 can correspond to amemory array region while the other regions 12 and 14 corresponds to aportion of the wafer peripheral to the memory array region.

[0020] An oxide layer 18 is formed over substrate 16. Oxide layer 18 cancomprise, for example, silicon dioxide and can be formed by chemicalvapor deposition over layer 16. Alternatively, if substrate 16 comprisessilicon (such as, for example, if substrate 16 is monocrystallinesilicon) a silicon dioxide layer 18 can be formed by oxidizing an uppersurface of substrate 16.

[0021] Nitrogen is shown being dispersed onto and within layer 18. Thenitrogen is preferably formed primarily at a surface of oxide layer 18.Layer 18 is preferably less than 50 Å thick, and in particularembodiments is about 40 Å thick. Preferably, an entirety of the nitrogenformed within layer 18 is at least 10 Å above substrate 16.Alternatively, substantially all of the nitrogen formed within layer 18is preferably at least 10 Å above substrate 16. For purposes ofinterpreting this document and the claims that follow, it is to beunderstood that the reference to “substantially all” of the nitrogenwithin silicon dioxide layer 18 being at least 10 Å above substrate 16is defined to indicate that no measurable amount of nitrogen is in theportion of layer 18 that is within 10 Å of substrate 16. In particularembodiments of the present invention, substantially all of the nitrogenformed within layer 18 is formed within the top 10 Å of layer 18. Inother words, no measurable amount of nitrogen extends below the top 10 Åof layer 18, which can, in particular embodiments, indicate that anentirety of the nitrogen is within the top 10 Å of layer 18.

[0022]FIGS. 8 and 9 illustrate apparatuses which can be utilized forforming nitrogen within only the upper portions of silicon dioxide layer18. Referring to FIG. 8, nitrogen-comprising region 22 can be formed byremote plasma nitridization utilizing an apparatus 200. Apparatus 200comprises a plasma chamber 202 and a reaction chamber 204. Reactionchamber 204 comprises a substrate holder 206, and substrate 16 issupported within chamber 204 by holder 206. Preferably, holder 206 isconfigured to rotate substrate 16 during exposure of substrate 16 toactivated nitrogen species. Such activated nitrogen species are formedwithin plasma chamber 202 by, for example, exposing N₂ and/or othernitrogen-containing materials (such as N₂O or NH₃) to plasma conditions,with the term “activated” indicating that the nitrogen species isdifferent than the form of nitrogen fed to the plasma. An activatednitrogen species can comprise, for example, a nitrogen ion or a nitrogenatom in an energy state higher than its ground state. Exemplary plasmaconditions comprise utilization of a microwave plasma generator at apower of from about 1,500 watts to about 3,000 watts, and utilizing apressure within chamber 202 of less than or equal to about 3 Torr. Theplasma of chamber 202 forms activated nitrogen species which migratealong a passageway 208 into chamber 204 whereupon the species can form anitrogen-comprising layer over and within oxide 18 (FIG. 1).

[0023] An arrow is shown within passageway 208 to indicate migration ofplasma activated nitrogen species through passageway 208. Preferably,passageway 208 is of sufficient length so that plasma 202 is at leastabout 12 inches from substrate 16. Such can enable highly activatednitrogen species formed within a plasma to relax prior to interactionwith substrate 16, which can limit penetration of the nitrogen speciesinto substrate 16 relative to an amount of penetration which would occurwith more highly activated species. In order to further limitpenetration of nitrogen species into substrate 16, substrate 16 ispreferably not biased relative to the plasma within chamber 202.

[0024] Suitable operating conditions for forming a nitrogen-comprisingplasma over substrate 16 can include maintaining a temperature ofsubstrate 16 at from about 550° C. to about 1,000° C., rotating thewafer at about 90 rotations per minute (RPM), maintaining a pressurewithin chambers 202 and 204 of from about 0.8 Torr to about 2.8 Torr,and exposing the wafer to the nitridization conditions for from aboutone minute to about five minutes.

[0025] An alternative apparatus which can be utilized for formingnitrogen over and within oxide layer 18 (FIG. 1) is described withreference to FIG. 9 as apparatus 220. Apparatus 220 can be referred toas a high density plasma remote plasma nitridization (HDP-RPN)apparatus, or simply as a plasma nitridization (PN) apparatus. Apparatus220 comprises a reaction chamber 222 having a wafer holder 224 therein.Wafer 16 is supported on holder 224. A plasma 226 is formed abovesubstrate 16, and preferably is maintained a distance “X” from substrate16, with distance “X” corresponding to at least about four inches.Nitrogen is introduced into plasma 226 in the form of, for example, N₂,and activated nitrogen species are formed from the nitrogen. Suitableprocessing parameters for utilization of the apparatus of FIG. 9 includea wafer temperature of from 0° C. to 400° C., no rotation of thesubstrate 16, a pressure within chamber 222 of from about 5 mTorr toabout 15 mTorr (preferably of from about 5 mTorr to about 10 mTorr), andan exposure time of substrate 16 to activated nitrogen species withinchamber 222 of from about 5 seconds to about 30 seconds.

[0026] Referring next to FIG. 2, a conductive layer 20 is formed overoxide 18, and a patterned masking layer 22 is formed over the portion ofconductive layer 20 that is associated with region 12, while the portionof conductive layer 20 associated with region 14 remains exposed.

[0027] Conductive material 20 can comprise, for example, conductivelydoped silicon, such as, for example, conductively doped amorphous orpolycrystalline silicon. In particular embodiments of the presentinvention, conductive layer 20 comprises p-type doped silicon.Conductive material 20 can also comprise metals, and/or silicides, inaddition to, or alternatively to, the conductively doped silicon.

[0028] Masking layer 22 can comprise, for example, photoresist, and canbe patterned by photolithographic processing.

[0029] Referring to FIG. 3, wafer fragment 10 is shown after beingexposed to etching conditions which remove layers 20 and 18 from overregion 14 of substrate 16. Masking layer 22 (FIG. 2) protects layers 18and 20 from being removed over region 12 of substrate 16. In embodimentsin which oxide 18 comprises silicon dioxide and conductive material 20comprises conductively doped silicon, a suitable etchant for removingmaterials 18 and 20 from over substrate 16 can comprise, for example,CF₄ and O₂.

[0030] It is noted that the structure shown in FIG. 3 can be obtainedthrough processing methods other than that shown in FIGS. 1-3. Forinstance, region 14 can be covered during formation of oxide layer 18and conductive layer 20, and subsequently the cover removed from overregion 14 to form a structure identical to that shown in FIG. 3.

[0031] Referring to FIG. 4, wafer 10 is shown after being exposed tooxidizing conditions. The oxidizing conditions form an oxide layer 24over substrate 16, and also form an oxide layer 26 over conductivematerial 20. If substrate 16 comprises monocrystalline silicon andconductive material 20 comprises conductively doped silicon, oxidelayers 24 and 26 will comprise silicon dioxide. Oxide layers 24 and 26can be formed by methods other than oxidation of layer 20 and substrate16, such as, for example, by chemical vapor deposition of silicondioxide. Also, it is noted that the invention encompasses embodimentswherein oxide is not formed over layer 20, such as, for example,embodiments in which oxide layer 24 is formed by oxidation of substrate16 and in which layer 20 comprises a non-oxidizable material.

[0032] Oxide layer 24 can be formed to be a different thickness thanoxide layer 18. For instance, oxide layer 18 can be optimized forformation of a PMOS transistor, and accordingly can be less than 50 Åthick, and, for example, about 40 Å thick, while oxide layer 24 can beoptimized for formation of an NMOS transistor, and accordingly can begreater than 50 Å thick, and, for example, can be about 70 Å thick.

[0033] Referring to FIG. 5, a second conductive material 28 is formedover regions 12 and 14 of substrate 16. Conductive material 28 cancomprise, for example, conductively doped silicon, and in particularembodiments comprises n-type doped silicon. Conductive material 28 cancomprise other conductive materials in addition to, or alternatively to,conductively doped silicon, such as, for example, metals and/orsilicides.

[0034] Referring to FIG. 6, wafer 10 is exposed to planarizingconditions which planarize an upper surface of wafer 10 and removelayers 26 and 28 from over first conductive layer 20. Exemplaryplanarizing conditions comprise chemical-mechanical polishing.Alternatively or in combination with the chemical-mechanical polishing,a polysilicon dry etch can be utilized to remove polysilicon from overboth of regions 12 and 14. A suitable polysilicon dry etch is anisotropic etch utilizing HBr.

[0035] Referring to FIG. 7, layers 18 and 20 are incorporated into afirst transistor structure 40 and layers 24 and 28 are incorporated intoa second transistor structure 42.

[0036] First transistor structure 40 comprises a silicide layer 44 andan insulative layer 46 which are formed over layers 18 and 20 andpatterned together with layers 18 and 20 to form a gate structure.Silicide layer 44 can comprise, for example, titanium silicide ortungsten silicide.

[0037] Second transistor structure 42 comprises a silicide layer 48 andinsulative layer 50 which are formed over layers 24 and 28 and patternedwith layers 24 and 28 to form a gate structure. Silicide layer 48 cancomprise, for example, titanium silicide or tungsten silicide, andinsulative layer 50 can comprise, for example, silicon nitride.

[0038] Sidewall spacers 52 are shown formed along sidewalls of patternedmaterials 24, 28, 48 and 50, as well as along sidewalls of patternedmaterials 18, 20, 44 and 46. Spacers 52 comprise insulative materials,and can comprise, for example, silicon dioxide or silicon nitride.

[0039] It is noted that although conductive layers 44 and 48 are shownseparately from conductive materials 20 and 28, silicides 44 and 48could also have been incorporated into conductive materials 20 and 28,respectively. In other words, conductive material 20 could, inparticular embodiments, encompass two layers, with a lower layercomprising conductively doped silicon and an upper layer comprising asilicide; and similarly conductive material 28 could, in particularembodiments, encompass two layers with a lower layer comprisingconductively doped silicon and an upper layer comprising a silicide.

[0040] Lightly doped diffusion (Ldd) regions 54 are shown within region12 of substrate 16, and source/drain regions 56 are also shown withinregion 12 of substrate 16. Source/drain regions 56 comprise p-typedopant and together with Ldd regions 54 and layers 18, 20, 44 and 46define a PMOS transistor 40. Lightly doped diffusion regions 54typically comprise p-type dopant.

[0041] Lightly doped diffusion regions 58 are shown within region 14 ofsubstrate 16 and heavily doped source/drain regions 60 are also shownwithin region 14 of substrate 16. Heavily doped source/drain regions 60comprise n-type dopant, and together with layers 24, 28, 48 and 50define NMOS transistor 42. Lightly doped diffusion regions 58 typicallycomprise n-type dopant.

[0042] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming a structure over a semiconductor substrate,comprising: forming a silicon dioxide containing layer across at leastsome of the substrate; providing nitrogen within the silicon dioxidecontaining layer, substantially all of the nitrogen within the silicondioxide being at least 10 Å above the substrate; and after providing thenitrogen within the silicon dioxide containing layer, formingconductively doped silicon on the silicon dioxide layer.
 2. The methodof claim 1 wherein the silicon dioxide layer is at least 30 Å thick, andwherein substantially all of the nitrogen is provided in the top 10 Å ofthe silicon dioxide layer.
 3. The method of claim 1 wherein the nitrogenis provided within the silicon dioxide layer from plasma activatednitrogen species.
 4. The method of claim 1 wherein the nitrogen isprovided within the silicon dioxide layer by remote plasma nitridizationutilizing nitrogen species generated in a plasma that is at least about12 inches from the substrate.
 5. The method of claim 1 wherein thenitrogen is provided within the silicon dioxide layer by remote plasmanitridization utilizing nitrogen species generated in a plasma that isat least about 12 inches from the substrate; the plasma being generatedin a chamber from N₂, at a power of from about 1500 watts to about 3000watts, and a pressure of from about 0.5 Torr to about 3 Torr; thesubstrate not being biased relative to the plasma during provision ofthe nitrogen within the silicon dioxide layer.
 6. The method of claim 5wherein the substrate is maintained at a temperature of from about 550°C. to about 1000° C. during provision of the nitrogen within the silicondioxide layer.
 7. The method of claim 5 wherein the substrate is exposedto the nitrogen species for a time of from greater than 0 minutes toabout about 5 minutes.
 8. The method of claim 1 wherein the nitrogen isprovided within the silicon dioxide layer by plasma nitridizationutilizing nitrogen species generated in a plasma that is at least about4 inches from the substrate.
 9. The method of claim 8 wherein thesubstrate is maintained at a temperature of from about 550° C. to about1000° C. during provision of the nitrogen within the silicon dioxidelayer.
 10. The method of claim 8 wherein the substrate is exposed to thenitrogen species for a time of from greater than 0 minutes to aboutabout 5 minutes.
 11. A method of forming structures over a semiconductorsubstrate, comprising: forming a first oxide region which covers only aportion of the substrate; providing nitrogen within the first oxideregion, substantially all of the nitrogen within the first oxide regionbeing at least 10 Å above the substrate; forming a second oxide regionover at least some of the substrate which is not covered by the firstoxide region; forming a first conductively-doped silicon material overthe first oxide region and a second conductively-doped silicon materialover the second oxide region; one of the first and secondconductively-doped silicon materials being n-type doped and the otherbeing p-type doped.
 12. The method of claim 11 wherein the nitrogen isprovided within the first oxide region from plasma activated nitrogenspecies.
 13. The method of claim 11 wherein the second oxide region isthicker than the first oxide region.
 14. The method of claim 11 whereinthe p-type doped silicon material is formed over the first oxide region.15. The method of claim 11 wherein the p-type doped silicon material isformed over the first oxide region, and is formed before forming thesecond oxide region.
 16. The method of claim 15 wherein the second oxideregion is formed by oxidizing the substrate, and wherein the oxidizingalso oxidizes the p-type doped silicon material to form a third oxideregion over the p-type doped silicon material.
 17. The method of claim11 wherein: the p-type doped silicon material is formed over the firstoxide region, and is formed before forming the second oxide region; thesecond oxide region is formed by oxidizing the substrate, and whereinthe oxidizing also the oxidizes the p-type doped silicon material toform a third oxide region over the p-type doped silicon material; andthe n-type doped silicon material is formed over the second and thirdoxide regions.
 18. The method of claim 17 further comprising removingthe n-type doped silicon material and third oxide layer from over thep-type doped silicon material.
 19. The method of claim 17 furthercomprising removing the n-type doped silicon material and third oxidelayer from over the p-type doped silicon material by chemical-mechanicalplanarization.
 20. The method of claim 17 further comprising: removingthe n-type doped silicon material and third oxide layer from over thep-type doped silicon material; patterning the p-type doped siliconmaterial into a first transistor gate; patterning the n-type dopedsilicon material into a second transistor gate; forming firstsource/drain regions proximate the first transistor gate to define afirst transistor comprising the first source/drain regions and firsttransistor gate; and forming second source/drain regions proximate thesecond transistor gate to define a second transistor comprising thefirst source/drain regions and first transistor gate.
 21. A method offorming a pair of transistors associated with a semiconductor substrate,comprising: defining a first region and a second region of thesubstrate; forming a first oxide region which covers at least some ofthe first region of the substrate and which does not cover the secondregion of the substrate; providing nitrogen within the first oxideregion; after providing the nitrogen within the first oxide region,forming a first conductive layer over the first oxide region and whichdoes not cover the second region of the substrate; after forming thefirst conductive layer, forming a second oxide region over the secondregion of the substrate; forming a second conductive layer over thesecond oxide region; patterning the first conductive layer into a firsttransistor gate; patterning the second conductive layer into a secondtransistor gate; forming first source/drain regions proximate the firsttransistor gate and gatedly connected to one another by the firsttransistor gate; and forming second source/drain regions proximate thesecond transistor gate and gatedly connected to one another by thesecond transistor gate.
 22. The method of claim 21 wherein the secondoxide region is thicker than the first oxide region.
 23. The method ofclaim 21 wherein the first and second conductive layers compriseconductively doped silicon.
 24. The method of claim 21 wherein the firstand second conductive layers comprise conductively doped silicon, thefirst conductive layer comprising p-type doped silicon and the secondconductive layer comprising n-type doped silicon.
 25. The method ofclaim 21 wherein the first and second conductive layers compriseconductively doped silicon, wherein the substrate is oxidized to formthe second oxide region, and wherein the first conductive layer isoxidized during formation of the second oxide region.
 26. The method ofclaim 21 wherein the first and second conductive layers compriseconductively doped silicon, wherein the substrate is oxidized to formthe second oxide region, wherein the first conductive layer is oxidizedduring formation of the second oxide region, wherein the secondconductive layer is formed over the oxidized first conductive layer; andwherein the second conductive layer is removed from over the oxidizedfirst conductive layer prior to patterning the first conductive layerinto a transistor gate.
 27. The method of claim 21 wherein the nitrogenis provided within the first oxide region from plasma activated nitrogenspecies.
 28. The method of claim 21 wherein the second oxide region isthicker than the first oxide region.
 29. The method of claim 21 whereinthe p-type doped silicon material is provided over the first oxideregion.
 30. The method of claim 21 wherein the p-type doped siliconmaterial is formed over the first oxide region, and is formed beforeforming the second oxide region.
 31. The method of claim 21 wherein thesubstrate comprises monocrystalline silicon and the oxide regionscomprise silicon dioxide; and wherein the first and second oxide regionsare grown from the monocrystalline silicon substrate.
 32. Asemiconductor assembly, comprising: a semiconductor substrate having afirst region and a second region defined therein; a first oxide regionon the substrate and covering the first region of the substrate; thefirst oxide region having nitrogen provided therein; substantially allof the nitrogen being at least 10 Å above the semiconductor substrate; afirst conductive layer over the first oxide region and defining a firsttransistor gate; first source/drain regions proximate the firsttransistor gate and gatedly connected to one another by the firsttransistor gate; and a second oxide region covering the second region ofthe substrate; a second conductive layer over the second oxide regionand defining a second transistor gate; second source/drain regionsproximate the second transistor gate and gatedly connected to oneanother by the second transistor gate.
 33. The assembly of claim 32wherein substantially all of the nitrogen is within a top 10 Å of thefirst oxide region.
 34. The assembly of claim 32 wherein the secondoxide region is thicker than the first oxide region.
 35. The assembly ofclaim 32 wherein the first conductive layer comprises p-type dopedsilicon and the second conductive layer comprises n-type doped silicon.